What are important signals of 8086? Discuss them in brief.

Answer:

The 8086 signals can be categorized in three groups. The first are the signals having' common functions in minimum as well as maximum mode, the second are the signals which have special functions in minimum mode and third are the signals having special functions tor maximum mode.

The following signal descriptions are common for both the minimum and maximum modes

AD15-AD0:-

These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1state. while the data is available on the data bus during T₂. T₃, T_w and T₄. Here T₁, T₂. T₃, T₄ and T₄ are the clock states of machine cycle. Tw is a wait state. These lines are active high and float to a tri state during interrupt acknowledge and local bus hold acknowledge cycles.

A/3/s6, A/8/s5,A17/S4, A16/Sc:-

These are the time multiplexed address and slams lines during T1, these are the most significant address lines or memory operators. During I/O or I/O Operations. Status information is available on those lines for T₂, T₃, T_u and T₄. The status of the interrupt enable flag bit (displayed on S5) is updated at the beginning of each clock cycle. The S4 and S₃ Combined indicate which segment register presently being used for .memory accesses as shown in Table:-

These lines float to tri-state off (tristaed) during the local bus hold acknowledge. The status line S₆ is always low (logical). The address bits are separated from the status bits using latches controlled by the ALE signal

S₄	S₃	Indication
0	0	Alternate Date
0	0	Stack
1	0	Code or none
1	1	Data

BHE/S7-Bus High Enable/status:-

The bus high enable signal is used to indicate the transfer of data over the higher order (D₁₅-D₈). Data bus as shown in table. It goes low for the data transfers over D₁₅-D₈ and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on the higher byte of the data bus, The status information is available during T₂, T₃ and T₄. The signal is active low and is tristated during hold. It is low during T₁ for the first pulse of the interrupt acknowledge cycle.

BHE	AO	Indication
0	0	Whole word
0	1	Upper byte from or to 0 odd address
1	0	Upper byte from or to even address
1	1	None

RD-Read: Read signal, When low, indicates the peripherals that the pm: is performing a memory or I/O read operation. RD is active low and shows the state for T₂, T₃, T_w of any mad cycle, The signal remains this stated during the ‘hold‘ acknowledge.

READY: This is the acknowledgement from the slow devices or memory that they have completed the data transfer.

INTR-Interrupt request:- This is a level triggered input. This is sampled during clock cycle of each instruction to determine the availability of the request.

TEST:- This input is examined by a ‘WAIT‘ instruction. If the TEST input goes low, execution will continue else the processor remains in an idle state.

NMI-Non-Maskable Interrupt: This is an edge triggered input which causes a type 2 interrupt. The NMI is not maskable internally by software.

RESET: This input causes the processor to terminate the current activity and start execution from FFFF OH.

CLK-Clock Input:- The clock input provides the basic timing for processor operation and bus control activity.

VCC: t5y power supply for the operation of the internal circuit. GND ground for the internal circuit.

MN/MX:- The logic level at this pin deem whether the processor is to operate in either minimum (single processor) or maximum (multiprocessor) mode.

MN/IO- Memory/IO:- This is a status line logically equivalent to S2 in maximum mode when it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation.

INTA- Interrupt Acknowledge:- This w signal is used as a read strobe for interrupt acknowledge cycles.

ALE- Address latch Enable:- This output signal indicates the availability of th¢ valid address on the address data lines and is connected to latch enable input of latches.

DT/R-Data Transmit/Receive:- This output is used to decide of data flow through Tran receivers.

DEN-Data Enable:- This signal indicates the availability of valid over the lines.