Explain with the block diagram of hardware addition and subtraction.

Figure suggests the data paths and hardware element needed to accomplish addition and subtraction. The central element is a binary adder, which is presented two numbers for additional and produces a sum and an overflow indication. The binary adder treats the two numbers as unsigned integers. For addition, the two numbers are presented to the adder form two registers, designated in this case as A and B registers.

The result may be stored in one of these registers or in a third. The over flow indication is stored in a 1-bit overflow flag (0= no overflow; 1= overflow). For subtraction, the subtrahend (B register) is passed through a two’s complemented so that it’s two’s complemented is presented to the adder. Note that figure only shows the data paths. Control signals are needed to control whether or not the complemented is used, depending on whether the operation is addition or subtraction.