Show how a Direct Memory Access (DMA) controller device can be connected in an 8086 system and discuss how a DMA data transfer takes place.

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows the device to transfer the data directly to/ from memory without any interference of the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

The 8237 DMA controller as the example for this section because it is a commonly used device also. It is one of the devices you will friend if you start poking around inside an IBM PC/XT or PC/AT. Before we dig into the actual connections and operation of an 8237 circuit, however, let's take a look at the block diagram in Fig to get an overview of how a DMA transfer takes plate. The main point to keep in your mind here is that the microprocessor and the DMA controller timeshare the use of the address, data, and control buses. The three switches in the middle of the block diagram are an attempt to show how central of the buses is transferred. When the System is first turned on, the switches are in the up position, so the buses are connected 'from the microprocessor to system memory and peripherals. We initialize all the programmable devices in the system and go on executing our program until we need, for example to read a file off a disk. To read a disk file we send a series of commands to the smart disk controller device, telling it to find and read the desired block of data from the disk. When the disk controller has the first byte of data from the disk block ready it sends a DMA request, DREQ, signal to the DMA controller. If that input (channel) of the DMA controller is unmasked, the DMA controller win send a hold-request HRQ signal to the microprocessor HOLD input. The microprocessor will respond to this input by peripheral device.