Describe dedicated interrupts.
An interrupt is a special condition
that, arises during the working of a microprocessor. The microprocessor
services it by executing a subroutine called Interrupt Service Routine (ISR).
Dedicated
interrupts:
(i)
Type 0: Divide by Zero Interrupt:
·
8086 supports division (unsigned/signed)
instruction. 8086 will automatically do a type 0 interrupt if the result of DIV
or IDIV operation is too large to fit in destination register.
·
When type 0 interrupt is internally
generated, microprocessor will.
o Push
flag register.
o Reset
TF and IF.
o Push
CS and IP (i.e. return address).
o Get
NEW CS and NEW IP. For this, microprocessor takes type no i.e. ‘0', multiply by
4. Therefore we get 0 × 4 = 000H. So microprocessor gets NEW IP from
00000H/00001H location and NEW CS from 00002H/00003H location.
o NEW
CS and NEW IP will be loaded into the CS and IP register. Thus we get branching
to ISR routine.
o After
returning from ISR, microprocessor will pop CS and IP (OLD CS/OLD IP)
Microprocessor will also pop flag register.
Type 0 is automatic and cannot be
disabled i.e. non-mask-able.
Users have to account It in the
program where he/she uses DIV/IDIV instruction.
Normally user will write an interrupt
service procedure which takes desired action when an invalid division occurs.
To avoid this interrupt, user can
check before division that divisor is not zero.
(ii)
Type 1: Single Step Interrupt (INT1):
·
The microprocessor executes this interrupt
after every instruction if the TF is set.
·
It puts microprocessor in single stepping
mode he the microprocessor pauses after executing every instruction. This is
very useful during debugging.
·
Its ISR generally displays contents of all
registers. Its ISR address is stored at location 1 × 4 = 00004H in the IVT.
(iii)
Type 2: NMI (Non-Mask-able Interrupt) (INTZ):
·
This is the highest priority hardware
interrupt and is non-mask-able. The input is edge triggered but is synchronized
with the CPU clock and must be active for two clock cycles to generate
recognition.
·
The interrupt signal may be removed, prior
to entry to the service routine.
·
Since the input must make a LOW to HIGH
transition to generate an interrupt, spurious transition on the input should be
suppressed.
·
If the input is normally HIGH, the NMI low
time to guarantee triggering is two CPU clock times.
·
Its ISR address IS stored at location 2 ×
4 = 00008H in the Interrupt Vector Table (IVT).
·
Basically NMI interrupt input is used for
catastrophic failures for example power failure, time out of system watchdog
timer.
(iv)
Type 3: One Byte Interrupt/Breakpoint Interrupt (INT3):
·
This type is invoked by a special form of
the software interrupt instruction which requires a single byte of code space
i.e. CCH (INT3).
·
This interrupt is primarily used as a
breakpoint interrupt for software debug.
·
When we insert a breakpoint in program,
the system executes instructions up to the breakpoint and then goes to the
breakpoint procedure.
·
When user informs debugger program to
insert breakpoint at some point in program, they actually do it by temporarily
replacing the instruction byte at that address with CCH i.e. code for INT3
instruction.
·
Thus this single byte instruction can be
mapped into the smallest instruction for absolute resolution in setting
breakpoints.
·
Its ISR address is stored at location 3 ×
4 = 0000CH in the IVT.
·
A breakpoint ISR routine usually saves all
the register contents on the stack.
(v)
Type 4: Interrupt on Overflow (INTO):
·
This interrupt occurs if the overflow flag
(OF) is set in the flag register.
·
The OP flag is set if the signed result of
an arithmetic operation on two signed number is too large to be represented in
destination register or memory location. Thus this interrupt is used to capture
overflow errors.
·
Its ISR address is stored at location 4 ×
4 = 00010H in the IVT.
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